IBIS Macromodel Task Group

Meeting date: 26 July 2022

Members (asterisk for those attending):
Achronix Semiconductor:       Hansel Dsilva
Amazon:                       John Yan
ANSYS:                      * Curtis Clark
                            * Wei-hsing Huang
Cadence Design Systems:     * Ambrish Varma
                              Jared James
Google:                     * Zhiping Yang
Intel:                        Michael Mirmak
                            * Kinger Cai
                            * Chi-te Chen
                              Alaeddin Aydiner
Keysight Technologies:        Fangyi Rao
                              Majid Ahadi Dolatsara
                              Ming Yan
                              Radek Biernacki
                              Rui Yang
Luminous Computing            David Banas
Marvell                       Steve Parker
Mathworks (SiSoft):         * Walter Katz
                              Mike LaBonte
Micron Technology:          * Randy Wolff
                              Justin Butterfield
Missouri S&T                  Chulsoon Hwang
SAE ITC                       Michael McNair
Siemens EDA (Mentor):       * Arpad Muranyi
Teraspeed Labs:             * Bob Ross
Zuken USA:                  * Lance Wang

The meeting was led by Arpad Muranyi.  Curtis Clark took the minutes.

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Opens:

- The meeting scheduled for August 2nd, 2022, will not be held because of the
  IEEE EMC+SIPI IBIS Summit occurring that week (see vote below).

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Review of ARs:

- None.

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Call for patent disclosure:

- None.

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Review of Meeting Minutes:

Arpad asked for any comments or corrections to the minutes of the July 19th
meeting.  Randy moved to approve the minutes.  Bob seconded the motion.
There were no objections.

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New Discussion:

IEEE EMC+SIPI IBIS Summit:
Arpad noted the Kinger would be presenting on the SPIM topic.

Zhiping said he would also be presenting at the summit.  He said in future ATM
meetings he could share a proposal for a new diode model in IBIS.  He said they
were also working on models for other key PI components including inductors,
FETs, controllers, and sinks, and they're trying to utilize existing keywords.
He said the SPIM work is part of the overall discussion.

Multi-level Analog Buffer Modeling:
Arpad reviewed the "GDDR6X IBIS Modeling" presentation he and Randy had given at
the 2021 IEEE EMC+SIPI IBIS Summit.  GDDR6X is a single-ended PAM4 interface,
and the presentation describes a prototype model with a Verilog-A implementation
in an [External Model].  4 I/V curves and 24 V-t waveforms were captured to
describe the PAM4 device's transitions, and the Verilog-A model implements the
multi-level transitions.  Arpad said some elements of the presentation might
help us as we consider multi-level analog signaling support in traditional non-
AMI IBIS models.

Bob asked whether Arpad's implementation itself showed that there's already a
solution in IBIS?  Arpad said not quite, and he noted that he'd had to use an
external file to specify the 4-state levels (i.e., each PAM4 symbol), as the
[External Model] only provides a two-level NRZ type logic input.  He'd merely
used the traditional [External Model] stimulus as a clock signal to clock in
the PAM4 symbols.  He said ideally it would be nice for IBIS to have a native
way to handle this multi-level symbol input.

Ambrish said Arpad's Verilog-A model offered one solution, and he said AMI can
support PAM4 already.  He asked why we are trying to do this in regular IBIS
when AMI can already handle it.  Walter agreed and asked what the point of
trying to do this in regular time-domain IBIS simulation would be.  He asked how
many bits you could simulate in this manner.  Randy said the point of the study
had been to investigate any differences between AMI simulations not capturing
non-linearities and traditional IBIS simulations.  He said all the I/V curves
capture non-linearities not captured by the AMI Tx model.  Arpad said the point
was not to compete with AMI in terms of the number of bits that could be
processed, but that AMI has some linearity assumptions that may not hold here.
Ambrish said some non-linearities were now captured by AMI.  Randy said a single
rising/falling response can't capture the impedance mismatches.  Randy said EDA
tools were doing a much better job of capturing non-linearities in NRZ with the
new multiple-edge techniques being employed.  However, he said even these did
not capture some of the non-linearities in this GDDR6X case.

Walter asked how lossy the channel was.  Randy said it might be 8 or 10 dB in
Nyquist range for a typical graphics channel.  Walter said that for a realistic
channel all these non-linearities in the Tx get washed out by the time you get
to the Rx.  Arpad noted that memory channels usually have less channel loss
than SERDES channels.  Walter said if you have a very low loss channel and
wide open eyes, then you'll see the differences in the eye plots from Tx non-
linearities such as edge rate variations for different transitions.  However,
for an engineer making decisions about a real-world channel, would this be an
important effect?  Walter said you'd really only need I/V curves for each of
the 4 levels.  Then, if you assume constant edge rates and use a sigmoid
function to transition between the levels, that would be sufficient for real
world applications.

Bob noted that an alternate approach using [Driver Schedule] to synthesize a
PAM4 Tx had been presented in, "Using [Driver Schedule] for PAM4 testing", at
the Asian IBIS Summits in November of 2021.  Per Walter's point, he said this
approach provided good agreement with Randy's results, and the channels filtered
out most of the differences in the Tx non-linearity modeling.  He said this
approach provided a simple solution that was already available in IBIS for EDA
tools supporting a full driver schedule implementation.  Arpad said that if we
are just going to assume that the channel will wash out all the effects, then we
may as well model the Tx with a Thevenin circuit and a perfect square wave.
Randy asked Arpad whether it would be sufficient if we were to add only the
multi-level stimulus to the specification.  Then a Verilog implementation could
get the stimulus directly from the simulator instead of using a two-level
stimulus to clock in the data from a file.  Arpad agreed.

Cancel Next Week's Meeting:
Bob moved to cancel the ATM meeting scheduled for August 2nd because the IEEE
EMC+SIPI symposium and IBIS Summit will be held that week.  Ambrish seconded.
There were no objections.

- Randy: Motion to adjourn.
- Ambrish: Second.
- Arpad: Thank you all for joining.
    
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Next meeting: 09 August 2022 12:00pm PT
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IBIS Interconnect SPICE Wish List:

1) Simulator directives
